The invention relates to the field of a microprocessorxe2x80x94coprocessor architecture. More particularly, it relates to the development of a software assembler tool for use with network processors in interfacing central processors with coprocessors.
The use of coprocessors with central processors in the design of a computer system processing complex architecture is well known. By assigning a task to a specific coprocessor, rather than requiring the central processor to perform the task, a processing complex designer may increase the efficiency and performance of a computer system. In order to add a coprocessor to a processor complex under prior art, a complex designer must program an assembler software tool that provides the hardware instructions required by the central processor to operate the coprocessor. However, a significant drawback to the efficient use of coprocessors is the need to rebuild the assembler software tool every time a coprocessor is changed or added. Accordingly, the finished design may not be changed to incorporate different or additional coprocessors without rebuilding the assembler software tool, where rebuilding involves reprogramming the assembler tool software.
The drawbacks of the prior art are solved by the development of a new assembler tool and associated processorxe2x80x94coprocessor architecture. This invention provides for a core language processor-coprocessor assembly comprising an assembler software tool for extending the base core language processor (CLP) tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself.
The addition of a coprocessor to a microprocessor or other central processor exposes the central processor programming model to a set of scalar registers, array registers and commands. The present invention provides for an assembler tool comprising a set of instructions within the microprocessor complex which manipulate the coprocessor registers, and a coprocessor execute command which initiates command processing on the coprocessor. The software component of the present invention is a special hardware command that executes among the coprocessors. The core language processor fetch""s that command from its processor memory, decodes the fact that it is intended to be executed on the coprocessor, and gives it to one of the coprocessors. The hardware component of the present invention is a unique CLP-coprocessor architecture that incorporates and enables the software embodiment. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling programmer""s to update their coprocessor definition files to reflect new or modified coprocessors. The assembler tool itself does not have to be rebuilt to track hardware changes associated with the addition of new coprocessors or modifications of existing ones.
The use of include files is standard prior art. What is new is the inclusion of a special assembler directive in the include files which describes a given coprocessor, the instructions available on the coprocessor, and the hardware registers that the coprocessor supports. The include file assembler directive describes to a core assembler the details of a specific coprocessor in such a way that the core assembler does not have to be rebuilt when the coprocessor is changed. The invention instructs the assembler program itself to recognize the new device. A programmer utilizing the invention supplies text input which specifies specific commands to be executed. The core assembler recognizes those commands and accordingly the correct syntax for those commands and generates the machine code for those commands.
The invention stabilizes the basic core language coprocessor instruction set and documentation associated with it. A further advantage is that the invention allows a hardware designer to test different xe2x80x9cwhat ifxe2x80x9d scenarios when considering the addition of a new coprocessors or modifications of existing ones, through the use of software simulators.